LC877264A Datasheet, PDF (10/24 Pages) Sanyo Semicon Device – 8-Bit Single Chip Microcontroller with 64/56/48 KB ROM and 2048-Byte RAM On Chip

Port Configuration
LC877264A/56A/48A
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Terminal
P00 to P07
Option applies to: Options
each bit
1
CMOS
Output Form
P10 to P17
P30 to P35
P70
P71 to P73
P80 to P87
S0/PA0 to
S47/PF7
each bit
each bit
–
–
–
–
2
1
2
1
2
None
None
None
None
Nch-open drain
CMOS
Nch-open drain
CMOS
Nch-open drain
Nch-open drain
CMOS
Nch-open drain
CMOS
Pull-up resistor
Programmable
(Note 1)
None
Programmable
Programmable
Programmable
None
Programmable
Programmable
None
Programmable
COM0/PL0 to
–
COM3/PL3
V1/PL4 to
–
V3/PL6
XT1
–
None Input only
None Input only
None Input only
None
None
None
XT2
–
None Output for 32.768kHz crystal
None
oscillation
Note 1 Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00-03, P04-07).
* Note 1: Connect as follows to reduce noise on VDD.
VSS1, VSS2 and VSS3 must be connected together and grounded.
*Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD3 as the power supply for ports. When the
VDD3 is not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore,
when the VDD3 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and
the back up time becomes shorter because the through current runs from VDD to GND in the input buffer.
If VDD3 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD
mode so that the port level becomes “L” level and unnecessary current consumption is prevented.
Power
supply
LSI
VDD1
Back-up capacitors *2 _VDD2
VDD3
VSS1 VSS2 VSS3
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