LE25FV101T Datasheet, PDF (1/10 Pages) Sanyo Semicon Device – 1M (128k words × 8bits) Serial Flash EEPROM

Preliminary Specifications
CMOS LSI
LE25FV101T
1M (128k words × 8bits) Serial Flash EEPROM
Features
CMOS Flash EEPROM Technology
Single 3.3-Volt Read and Write Operations
Sector Erase Capability: 256 Bytes per sector
Operating Frequency: 10MHz
Low Power Consumption
Active Current (Read): 25 mA (Max.)
Standby Current: 20 µA (Max.)
Serial Peripheral Interface (S.P.I.) mode 0.
High Read/Write Reliability
Sector-write Endurance Cycles: 10⁴
10 Years Data Retention
Self-timed Erase and Programming
Byte Programming: 35 µs (Max.)
End of Write Detection: Status Register Read
Hardware Data Protection
Packages Available: MSOP8(225mil)
Product Description
Device Operation
The LE25FV101T is a 128K x 8 CMOS sector
erase, byte programmable serial Flash EEPROM.
The LE25FV101T is manufactured using SANYO's
proprietary, high performance CMOS Flash
EEPROM technology. Breakthroughs in EEPROM
cell design and process architecture attain better
reliability and manufacturability compared with
conventional approaches. The LE25FV101T erases
and programs with a 3.3-volt only power supply.
LE25FV101T conforms to Serial Peripheral Interface
(S.P.I.).
Featuring high performance programming, the
LE25FV101T typically byte programs in 35 µs. The
LE25FV101T typically sector (256 bytes) erases in
4ms. Both program and erase times can be
optimized using interface feature such as Status
Register to indicate the completion of the write cycle.
To protect against an inadvertent write, the
LE25FV101T has on chip hardware data protection
scheme. Designed, manufactured, and tested for a
wide spectrum of applications, the LE25FV101T is
offered with a guaranteed sector write endurance of
10⁴ cycles. Data retention is rated greater than 10
years.
The LE25FV101T is best suited for applications
that require re-programmable nonvolatile mass
storage of program or data memory.
Commands are used to initiate the memory
operation functions of the device. Commands are
written to the command register through serial input
(SI). The addresses and data of Commands are
latched to be used to operate functions such as
Read, Sector_Erase, Byte_Program and so on.
Fig.3 and Fig.4 contain the timing waveforms of
serial input and output. By setting CS to LOW, the
device is selected. And commands, addresses, and
dummy bits can be let in serially through SI port.
When the device is in Read or Status Register Read
mode, SO pin is in Low-impedance state. And the
requested data can be read out from MSB (most
significant bit) synchronously with the falling edge of
SCK.
WP
1
Vcc
2
CS
3
SCK
4
8
RESET
7
Vss
6
SO
5
SI
Figure1: Pin Assignment for 8-pin MSOP
*This product incorporate technology licensed from Silicon Storage Technology, Inc.
This preliminary specification is subject to change without notice.
SANYO Electric Co., Ltd. Semiconductor Company
1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN
Revision c-November 1,1999-KI/ki-1/9