LC4102C Datasheet, PDF (1/8 Pages) Sanyo Semicon Device – LCD Dot Matrix Common Driver for STN Displays

Ordering number : EN5789A
CMOS LSI
LC4102C
LCD Dot Matrix Common Driver
for STN Displays
Overview
The LC4102C is a common driver for large-scale dot
matrix LCD panels. It includes a 160-bit bidirectional shift
register and 4-level LCD driver circuits. The number of
bits can be further increased by using the provided input
and output pins to connect multiple LC4102Cs in cascade.
The LC4102C and LC4104C form a large-screen LCD
panel driver chip set.
Features
• Fabricated in a CMOS (P-sub) high-voltage process.
• LCD drive voltage: 36 V
• Logic system power-supply voltage: 2.7 to 5.5 V
• fcp max: 2.5 MHz
• Slim chip (output pads are concentrated on one of the
longer sides)
• Bidirectional shift register
• The shift register can be split into two 80-bit registers.
(Two screens drivable)
• DISPOFF function that locks the drive voltages output
to the LCD at fixed levels.
• Display duty: 1/160 to 1/480
• Appropriate for COG (chip on glass) mounting. (A gold
bump structure is adopted in the pad areas.)
Specifications
The electrical characteristics values shown below are for devices packaged in the Sanyo standard PGA-208 package.
Absolute Maximum Ratings at V_SS = 0
Parameter
Symbol
Applicable pins
min
typ
max
Unit
Supply voltage
Input voltage
V_DD max
V_EE max
V_SS max
V_IN
V0, V1
V4
V5
V_DD
V_EE
V_SSH
*¹
V0, V1 *²
V4 *²
V5 *²
–0.3
–0.3
–0.3
–0.3
V_EE – 7.0
–0.3
–0.3
7.0
V
40.0
V
0.3
V
V_DD + 0.3
V
V_EE + 0.3
V
V_SS + 7.0
V
+0.3
V
Operating temperature
Topr
–20
+75
°C
Storage temperature
Tstg
–55
Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE
2. The voltages V0, V1, V4, and V5 must obey the relationships V_EE ≥ V0 ≥ V1 ≥ V_EE – 7 V, and 7 V ≥ V4 ≥ V5 ≥ V_SSH.
Allowable Operating Ranges at V_SS = 0, Ta = –20 to +75°C
+125
°C
Parameter
Symbol
Applicable pins
min
typ
max
Unit
V_DD
V_DD
2.7
5.5
V
Supply voltage
V_EE
V_EE
14
36
V
V_SSH
V_SSH
0
V
Input high-level voltage
V_IH
*¹
0.8 × V_DD
V_DD
V
Input low-level voltage
V_IL
*¹
0
0.2 × V_DD
V
V0, V1 V0, V1 *²
V_EE – 7.0
V_EE
V
Input voltage
V4
V4 *²
0
V_SSH + 7.0
V
V5
V5 *²
0
V
Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE
2. The voltages V0, V1, V4, and V5 must obey the relationships V_EE ≥ V0 ≥ V1 ≥ V_EE – 7 V, and 7 V ≥ V4 ≥ V5 ≥ V_SSH.
When turning on the power supplies, first turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively,
turn both on at the same time.
When turning off the power supplies, first turn off the high-voltage system power supply and then turn off the logic system power supply; alternatively,
turn both off at the same time.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
43098HA (OT)/82097HA (OT) No. 5789-1/8