STR-A6151M Datasheet, PDF (20/25 Pages) Sanken electric – Off-Line PRC Controllers with Integrated Power MOSFET

STR-A6100 Series
(2) Control Ground Trace Layout
Since the operation of IC may be affected from the
large current of the main trace that flows in control
ground trace, the control ground trace should be
separated from main trace and connected at a single
point grounding of point A in Figure 10-5 as close
to the R_OCP pin as possible.
(3) VCC Trace Layout: GND pin to C2 (negative) to T1
(winding D) to R2 to D2 to C2 (positive) to VCC pin
This is the trace for supplying power to the IC, and
thus it should be as small loop as possible. If C2 and
the IC are distant from each other, placing a
capacitor such as film capacitor C_f (about 0.1 μF to
1.0 μF) close to the VCC pin and the GND pin is
recommended.
(4) R_OCP Trace Layout
R_OCP should be placed as close as possible to the
S/OCP pin. The connection between the power
ground of the main trace and the IC ground should
be at a single point ground (point A in Figure
10-5) which is close to the base of R_OCP.
(5) FB/OLP Trace Layout
The components connected to FB/OLP pin should be
as close to FB/OLP pin as possible. The trace
between the components and FB/OLP pin should be
as short as possible.
(6) Secondary Rectifier Smoothing Circuit Trace
Layout: T1 (winding S) to D51 to C51
This is the trace of the rectifier smoothing loop,
carrying the switching current, and thus it should be
as wide trace and small loop as possible. If this trace
is thin and long, inductance resulting from the loop
may increase surge voltage at turning off the power
MOSFET. Proper rectifier smoothing trace layout
helps to increase margin against the power MOSFET
breakdown voltage, and reduces stress on the clamp
snubber circuit and losses in it.
(7) Thermal Considerations
Because the power MOSFET has a positive thermal
coefficient of R_DS(ON), consider it in thermal design.
Since the copper area under the IC and the D pin
trace act as a heatsink, its traces should be as wide as
possible.
C1
(7)Trace of D pin should be wid^DeST
for heat release
(1) Main trace should be wide
trace and small loop
(6) Main trace of secondary side should
be wide trace and small loop
T1
D51
C6
R1
P
C51
D1
S
87
5
D D NC ST
C5
U1
STR-A6100
S/OCP VCC GND FB/OLP
1
234
D2 R2
C2
D
(3) Loop of the power
supply should be small
R_OCP
A
DZ1
C4
PC1
C3
(5)The components connected to
FB/OLP pin should be as close
to FB/OLP pin as possible
C_Y
(4)ROCP should be as close to S/OCP pin as
possible.
(2) Control GND trace should be connected at a
single point as close to the ROCP as possible
Figure 10-5 Example of peripheral circuit around the IC
STR-A6100 - DS Rev.2.0
SANKEN ELECTRIC CO.,LTD.
20
Dec. 25, 2013