S5T8809 Datasheet, PDF (9/14 Pages) Samsung semiconductor – PLL FREQUENCY SYNTHESIZER FOR PAGER

PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
• Ex 1) FRC = 0, In case of 13bits Program, Fosc = 12.8MHz and 1/8 prescaler is used
[(Osc. Freq. / Prescaler) / Ref. Freq.] = [(12.8MHz / 8) / 6.25kHz] = 256
2¹²
2⁰
00001000000000001
MSB
LSB
LDC FRC TEST1 PMC bit
R - counter 13 - bits
• Ex 2) FRC = 1, In case of 15bits Program, Fosc = 12.8MHz and 1/8 prescaler is used
[Osc. Freq. / Ref. Freq.] = [12.8MHz / 6.25kHz] = 2048
2¹⁴
2 ¹²
2⁰
0001000000000000101
MSB
LSB
LDC FRC TEST1 PMC bit
R - counter 15 - bits
NOTE: The PMC bit is Program Mode Control Bit, if [1], the R-Counter will be Enabled
12.8MHz
X-Tal
OSCI
12.8MHz
D0 ------------- D13
1/8
1.6MHz
Prescaler
13/15 bits _Fr
Counter
6.25kHz
FRC
Figure 3. The architecture of R-Count Divider
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