K7R163682B Datasheet, PDF (9/20 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 & 2Mx9 QDRTM II b2 SRAM

K7R163682B
K7R161882B
K7R160982B
512Kx36 & 1Mx18 & 2Mx9 QDR^TM II b2 SRAM
STATE DIAGRAM
POWER-UP
READ NOP
READ
WRITE
WRITE NOP
READ
READ
LOAD NEW
READ ADDRESS
ALWAYS
(FIXED)
DDR READ
WRITE
READ WRITE
LOAD NEW
WRITE ADDRESS
ALWAYS
(FIXED)
WRITE
WRIDTDERPWORRTITNEOP
Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case.
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
Rev. 5.0 July 2006
-9-