K7K3236T2C Datasheet, PDF (9/19 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM

K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
K
LD
R/W
Stopped
X
X
DQ(A1)
Previous state
DQ
DQ(A2)
Previous state
↑
H
X
High-Z
High-Z
↑
L
H
QOUT at K(t+2)
QOUT at K(t+2)
↑
L
L
Din at K(t+1)
Din at K(t+1)
Notes: 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
OPERATION
Clock Stop
No Operation
Read
Write
WRITE TRUTH TABLE(x18)
K
K
BW0
BW1
↑
L
L
OPERATION
WRITE ALL BYTEs ( K↑ )
↑
L
L
↑
L
H
↑
L
H
↑
H
L
↑
H
L
WRITE ALL BYTEs ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 1 ( K↑ )
WRITE BYTE 1 ( K↑ )
↑
H
H
↑
H
H
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
WRITE TRUTH TABLE(x36)
K
K
BW0
BW1
BW2
BW3
OPERATION
↑
L
L
L
L
WRITE ALL BYTEs ( K↑ )
↑
L
L
L
L
WRITE ALL BYTEs ( K↑ )
↑
L
H
H
H
WRITE BYTE 0 ( K↑ )
↑
L
H
H
H
WRITE BYTE 0 ( K↑ )
↑
H
L
H
H
WRITE BYTE 1 ( K↑ )
↑
H
L
H
H
WRITE BYTE 1 ( K↑ )
↑
H
H
L
L
WRITE BYTE 2 and BYTE 3 ( K↑ )
↑
H
H
L
L
WRITE BYTE 2 and BYTE 3 ( K↑ )
↑
H
H
H
H
WRITE NOTHING ( K↑ )
↑
H
H
H
H
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
Rev. 1.3 August 2008
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