K4M563233G Datasheet, PDF (9/12 Pages) Samsung semiconductor – 2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA

K4M563233G - F(H)N/G/L/F
Mobile-SDRAM
SIMPLIFIED TRUTH TABLE
Register
Refresh
COMMAND
Mode Register Set
Auto Refresh
Self
Refresh
Entry
Exit
CKEn-1 CKEn
CS
RAS CAS
WE DQM BA0,1 A10/AP
A11,
A9 ~ A0
Note
H
X
LL
LL
X
OP CODE
1, 2
H
3
H
LL
LHX
X
L
3
LH HH
3
L
H
X
X
HX X X
3
Bank Active & Row Addr.
H
X
LL
HH X
V
Row Address
Read &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
Write &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
Burst Stop
H
Bank Selection
Precharge
H
All Banks
Clock Suspend or
Active Power Down
Entry
H
Exit
L
Precharge Power Down
Mode
Entry
H
Exit
L
X
LH
LHX
V
X
LH
LL
X
V
X LH HL X
V
X LL HLX
X
HX X X
L
X
LV VV
H XX XX X
HX X X
L
X
LH HH
HX X X
H
X
LV VV
L
Column 4
H
Address
(A0~A8)
4, 5
L
Column 4
H
Address
(A0~A8)
4, 5
X
6
L
X
H
X
X
DQM
No Operation Command
H
X
V
X
7
HX X X
H
X
X
X
LH HH
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
NOTES :
1. OP Code : Operand Code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
February 2006