English
Language : 

K4E661612C Datasheet, PDF (9/36 Pages) Samsung semiconductor – 4M x 16bit CMOS Dynamic RAM with Extended Data Out
K4E661612C,K4E641612C
16. tCWL is specified from W falling edge to the earlier CAS rising edge.
17. tCSR is referenced to earlier CAS falling before RAS transition low.
18. tCHR is referenced to the later CAS rising high after RAS transition low.
RAS
LCAS
UCAS
tCSR
tCHR
CMOS DRAM
19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle.
LCAS
UCAS
DQ0 ~ DQ15
tDS
tDH
Din
20. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
21. tASC≥6ns, Assume tT=2.0ns, if tASC≤6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC".
22. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
23. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
24. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and
after self refresh in order to meet refresh specification.