S5D2650 Datasheet, PDF (85/95 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D2650 Data Sheet
MULTIMEDIA VIDEO
Index
0x3E
Mnemonic
VSDEL
bit 7
TR_MS
bit 6
NOVIDC
VS Delay Control
bit 5
bit 4
bit 3
bit 2
VSDEL[5:0]
bit 1
bit 0
VSDEL[5:0]
NOVIDC
TR_MS
When the chip is programmed for digital video input operation, this register provides an offset
for the internal line counter to align with input video (VS can be either from the VS pin or from
embedded timing code). The register content is unsigned.
Allows NOVID bit to be output to PORTB (pin 24).
0
Normal operation.*
1
The NOVID bit is output to PORTB if DATAB[2:0]=1 and DIRB=1.
Enable alternative initial tracking mode state machine.
0
Normal operation - Horizontal tracking mode is controlled by the HFSEL[1:0] bits.*
1
Variable tracking modes during locking time.
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7/18/03