TL7231MD Datasheet, PDF (8/37 Pages) Samsung semiconductor – FULL LAYER-III ISO/IEC 11172-3 AUDIO DECODER

TL7231MD
FUNCTIONAL DESCRIPTION
RESET/CLOCK UNIT
TL7231MD is driven by a single clock at the frequency of 16.9344MHz. The clock is derived
from an external source or from an industry standard crystal oscillator, generating input
frequency of 16.9344MHz. The clock generation unit has a PLL, and all the internal clock
signals including internal DAC/ADC clocks are generated with the input clock.
When TL7231MD is in power-on-reset, RESET signal should be active at least 150µs till the
internal PLL is stabilized. To reset TL7231MD during normal operation, RESET signal should be
active at least 16 cycles.
TL7231MD
CPUXI
16.9344MHz
CPUXO
FILTER
820p
30p
1M
30p
Figure 3. Clock Circuit
DSP CORE LOGIC
The core logic of TL7231MD is a 32-bit floating-point DSP processor. The independent multiplier
and accumulator of TL7231MD can achieve high performance. Internal registers are 40-bit
registers that store values with a 32-bit mantissa and an 8-bit exponent. These registers can
serve as both the source and destination for any arithmetic operation. Since all the data
input/output transactions are managed by DMA, there is no computational overhead due to data
transactions.
SERIAL INTERFACE
The serial interface of TL7231MD is used to receive MPEG bit stream data or transmit/receive
voice data. It is configured to transfer 8 bits of data per word. It can be configured to be LSB-
first or MSB first transfer mode. LSB-first means that the data bits are transmitted and received
least-significant bit (LSB) first. MSB-first means that the data bits are transmitted and received
most-significant bit (MSB) first. The clock for the serial interface should be generated externally.
The related signals are CLKXRM, DXRM, and REQSTRM. REQSTRM is used for
synchronization between microcontroller and TL7231MD, and data is transferred during
REQSTRM active.
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SAMSUNG Electronics Co.