K7R323684M Datasheet, PDF (8/18 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 QDRTM II b4 SRAM

K7R323684M
K7R321884M
1Mx36 & 2Mx18 QDR^TM II b4 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
K
R
Stopped X
D
Q
W
OPERATION
D(A1)
D(A2)
D(A3)
D(A4)
Q(A1)
Q(A2)
Q(A3)
Q(A4)
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X
Clock Stop
state
state
state
state
state
state
state
state
↑
H
H
X
X
X
X
High-Z High-Z High-Z High-Z No Operation
↑
L⁴
X
X
X
X
X
D OUT
D OUT
D OUT
DOUT
Read
at C(t+1) at C(t+2) at C(t+2) at C(t+3)
↑
H⁵
L⁴
Din
Din
Din
Din
at K(t+1) at K(t+1) at K(t+2) at K(t+2)
X
X
X
X
Write
Notes: 1. X means "Don ′t Care".
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
4. This signal was HIGH on previous K clock rising edge. Initating consecutive READ or WRITE operations on consecuti ve K clock rising edges
is not permitted. The device will ignore the second request.
5. If this signal was LOW to inititate the previous cycle, this signal becomes a don′t care for this operation however it is strongly recommended
that this signal is brought HIGH as shown in the truth table.
WRITE TRUTH TABLE(x18)
K
K
B W0
BW1
OPERATION
↑
L
L
WRITE ALL BYTEs ( K↑ )
↑
L
L
↑
L
H
WRITE ALL BYTEs ( K↑ )
WRITE BYTE 0 ( K ↑ )
↑
L
H
↑
H
L
WRITE BYTE 0 ( K↑ )
WRITE BYTE 1 ( K ↑ )
↑
H
L
↑
H
H
WRITE BYTE 1 ( K↑ )
WRITE NOTHING ( K↑ )
↑
H
H
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
WRITE TRUTH TABLE(x36)
K
K
B W0
BW 1
B W2
BW 3
OPERATION
↑
L
L
L
L
↑
L
L
L
L
WRITE ALL BYTEs ( K↑ )
WRITE ALL BYTEs ( K↑ )
↑
L
H
H
H
↑
L
H
H
H
WRITE BYTE 0 ( K↑ )
WRITE BYTE 0 ( K↑ )
↑
H
L
H
H
↑
H
L
H
H
WRITE BYTE 1 ( K↑ )
WRITE BYTE 1 ( K↑ )
↑
H
H
L
L
↑
H
H
L
L
↑
H
H
H
H
WRITE BYTE 2 and BYTE 3 ( K↑ )
WRITE BYTE 2 and BYTE 3 ( K↑ )
WRITE NOTHING ( K↑ )
↑
H
H
H
H
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
-8-
Dec. 2003
Rev 2.0