K6R4016V1D Datasheet, PDF (8/12 Pages) Samsung semiconductor – 256Kx16 Bit High Speed Static RAM(3.3V Operating)

K6R4016V1D
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE Clock)
Address
OE
CS
UB, LB
WE
Data in
Data out
tWC
tAW
tCW(3)
tWR(5)
tBW
tAS(4)
tWP(2)
High-Z
tOHZ(6)
tDW
tDH
Valid Data
High-Z
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low fixed)
Address
CS
UB, LB
tAS(4)
tWC
tAW
tCW(3)
tBW
tWP1(2)
tWR(5)
WE
Data in
Data out
High-Z
tWHZ(6)
tDW
tDH
Valid Data
tOW
High-Z
(10)
(9)
-8-
Rev 4.0
Mar. 2004