K6F2008T2E Datasheet, PDF (8/9 Pages) Samsung semiconductor – 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM

K6F2008T2E Family
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
Address
CS1
CS2
WE
tAS(3)
tWC
tAW
tCW(2)
tWP(1)
Data in
Preliminary
CMOS SRAM
tWR(4)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
tSDR
2.7V
2.2V
VDR
CS1
GND
CS2 controlled
VCC
2.7V
CS2
tSDR
VDR
0.4V
GND
Data Retention Mode
CS1≥VCC - 0.2V
Data Retention Mode
CS2≤0.2V
tRDR
tRDR
8
Revision 0.0
June 2003