K4S641632F Datasheet, PDF (8/11 Pages) Samsung semiconductor – 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL

K4S641632F
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
- 50
- 55
- 60
- 70
- 75
- 1H
- 1L
Symbol
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
CLK cycle
time
CAS latency=3
tCC
CAS latency=2
5
5.5
6
7
7.5
10
10
1000
1000
1000
1000
1000
1000
1000 ns 1
-
-
-
-
10
10
12
CLK to valid
output delay
CAS latency=3
CAS latency=2
tSAC
4.5
-
5
-
5
-
6
5.4
6
-
6
6
6
ns 1,2
7
Output data
hold time
CAS latency=3
CAS latency=2
tOH
2
-
2
2.5
3
-
-
-
3
3
3
3
3
ns 2
3
CLK high pulse width
tCH
2
2
2.5
3
2.5
3
3
ns 3
CLK low pulse width
tCL
2
2
2.5
3
2.5
3
3
ns 3
Input setup time
tSS 1.5
1.5
1.5
2
1.5
2
2
ns 3
Input hold time
tSH
1
1
1
1
0.8
1
1
ns 3
CLK to output in Low-Z
tSLZ
1
1
1
1
1
1
1
ns 2
CLK to output ^{CAS latency=3}
in Hi-Z
CAS latency=2
tSHZ
4.5
-
5
-
5
-
6
5.4
6
-
6
6
6
ns
7
Notes : _{1. Parameters depend on programmed CAS latency.}
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
1.37
4.37
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Notes : _{1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.}
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
3
3
1,2
1,2
Rev.0.1 Sept. 2001