K4S560832C Datasheet, PDF (8/11 Pages) Samsung semiconductor – 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL

K4S560832C
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
CAS latency=3
CLK cycle time
tCC
CAS latency=2
CLK to valid
output delay
CAS latency=3
tSAC
CAS latency=2
Output data
hold time
CAS latency=3
tOH
CAS latency=2
CLK high pulse width
tCH
CLK low pulse width
tCL
Input setup time
tSS
Input hold time
tSH
CLK to output in Low-Z
tSLZ
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
tSHZ
-7C
Min Max
7.5
1000
7.5
5.4
5.4
3
3
2.5
2.5
1.5
0.8
1
5.4
5.4
-75
Min Max
7.5
1000
10
5.4
6
3
3
2.5
2.5
1.5
0.8
1
5.4
6
-1H
Min Max
10
1000
10
6
6
3
3
3
3
2
1
1
6
6
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
-1L
Min Max
10
1000
12
6
7
3
3
3
3
2
1
1
6
7
Unit Note
ns 1
ns 1,2
ns 2
ns 3
ns 3
ns 3
ns 3
ns 2
ns
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Output rise time
Symbol
Condition
Min
Typ
Max
trh
Measure in linear
region : 1.2V ~ 1.8V
1.37
4.37
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Notes : _{1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.}
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Unit
Volts/ns
Notes
3
Volts/ns
3
Volts/ns
1,2
Volts/ns
1,2
Rev. 0.1 Sept. 2001