M470L3224BT0 Datasheet, PDF (7/14 Pages) Samsung semiconductor – 256MB DDR SDRAM MODULE

M470L3224BT0
DDR SDRAM module I_DD spec table
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
Normal
Low power
IDD7A
A2(DDR266@CL=2)
typical
worst
620
680
760
840
320
340
380
420
360
380
380
400
440
480
1080
1240
1280
1460
960
1080
24
24
12
12
1700
1940
200pin DDR SDRAM SODIMM
B0(DDR266@CL=2.5)
typical
worst
620
680
760
840
320
340
380
420
360
380
380
400
440
480
1080
1240
1280
1460
960
1080
24
24
12
12
1700
1940
A0(DDR200@CL=2)
typical
worst
540
600
680
760
260
280
320
340
300
320
320
340
360
380
900
1040
1000
1140
880
960
24
24
12
12
1420
1640
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
Optional
* Module I_DD was calculated on the basis of component I_DD and can be differently measured according to DQ loading cap.
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.1 June. 2001