K4S643232H-TC70 Datasheet, PDF (7/12 Pages) Samsung semiconductor – 64Mb H-die (x32) SDRAM Specification

SDRAM 64Mb H-die (x32)
CMOS SDRAM
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System clock
CS
Chip select
CKE
Clock enable
A0 ~ A10
Address
BA0,1
Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 3 Data input/output mask
DQ0 ~ 31
VDD/VSS
Data input/output
Power supply/ground
VDDQ/VSSQ Data output power/ground
NC
No Connection
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
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Rev. 1.3 February. 2004