K4S511533F Datasheet, PDF (7/12 Pages) Samsung semiconductor – 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA

K4S511533F - Y(P)C/L/F
Mobile SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
-75
-1H
-1L
Unit
Note
Row active to row active delay
RAS to CAS delay
tRRD(min)
15
18
18
ns
1
tRCD(min)
18
18
24
ns
1
Row precharge time
tRP(min)
18
18
24
ns
1
Row active time
tRAS(min)
45
50
60
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
63
68
84
ns
1
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to Active delay
tDAL(min)
tRDL + tRP
-
3
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
Number of valid output data
Number of valid output data
tCCD(min)
CAS latency=3
CAS latency=2
1
CLK
4
2
1
ea
5
Number of valid output data
CAS latency=1
0
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
7
September 2004