DS_K4S161622D Datasheet, PDF (7/43 Pages) Samsung semiconductor – 1M x 16 SDRAM

K4S161622D-TI/E
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V^*2, Extended TA = -25 to +85°C , Industrial TA = -40 to +85°C)
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4 / 0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr / tf = 1 / 1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
Vtt=1.4V
Output
870Ω
1200Ω
50pF^*2
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Z0=50Ω
50Ω
50pF^*1
(Fig. 1) DC Output Load Circuit
Note : _{1. The DC/AC Test Output Load of K4S161622D-50/55/60/70 is 30pF.}
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
CAS Latency
CLK cycle time
CL
tCC(min)
Row active to row active delay
tRRD(min)
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to new col.address delay tCDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Mode Register Set cycle time
tMRS(min)
Number of valid output
data
CAS Latency=3
CAS Latency=2
-50
32
5 10
33
33
87
11 10
-55
32
5.5 10
33
33
77
10 10
Version
-60
-70
3232
6 10 7 10
2
3232
3232
7575
100
10 7 10 7
1
1
1
1
2
2
1
Unit
-80
-10
3 2 3 2 CLK
8 10 10 12 ns
CLK
3 2 2 2 CLK
3 2 2 2 CLK
6 5 5 4 CLK
us
9 7 7 6 CLK
CLK
CLK
CLK
CLK
CLK
ea
Note
1
1
1
1
1
2, 5
2
2
4
Notes : _{1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then}
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
Rev 1.2 Jan '03