K4S640832C Datasheet, PDF (6/11 Pages) Samsung semiconductor – 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL

K4S640832C
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Symbol
Test Condition
Burst length = 1
ICC1 tRC ≥ tRC(min)
IOL = 0 mA
CAS
Latency
-70
Version
-80 -1H -1L -10
Unit
Note
75 75 70 70 65 mA 1
Precharge standby current in
power-down mode
ICC2P CKE ≤ VIL(max), tCC = 15ns
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
1
mA
1
Precharge standby current in
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
12
non power-down mode
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
6
mA
Active standby current in
power-down mode
ICC3P CKE ≤ VIL(max), tCC = 15ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
2
mA
2
Active standby current in
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
20
mA
non power-down mode
(One bank active)
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
10
mA
Operating current
(Burst mode)
Refresh current
Self refresh current
IOL = 0 mA
ICC4
Page burst
2Banks activated
tCCD = 2CLKs
ICC5 tRC ≥ tRC(min)
ICC6 CKE ≤ 0.2V
Notes : _{1. Measured with outputs open.}
2. Refresh period is 64ms.
3. K4S640832C-TC**
4. K4S640832C-TL**
3
110 95 75 75 75
mA 1
2
75 75 75 70 70
125
110 mA 2
C
1
mA 3
L
450
uA
4
Rev.0.1 Oct.1999