K4S560832D Datasheet, PDF (6/11 Pages) Samsung semiconductor – 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL

K4S560832D
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Operating current
(One bank active)
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0 mA
Precharge standby cur-
rent in power-down mode
Precharge standby cur-
rent in non power-down
mode
ICC2P
ICC2PS
ICC2N
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P
ICC3PS
ICC3N
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
Operating current
(Burst mode)
IO = 0 mA
ICC4 ^{Page burst}
4banks Activated.
tCCD = 2CLKs
Refresh current
ICC5 tRC ≥ tRC(min)
Self refresh current
ICC6 CKE ≤ 0.2V
C
L
Version
Unit Note
-7C -75 -1H -1L
100 90 90 90 mA 1
2
mA
2
20
mA
10
6
mA
6
30
mA
25
mA
110 110 100 100 mA 1
220 200 190 190 mA 2
3
mA 3
1.5
mA 4
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S560832D-TC**
4. K4S560832D-TL**
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev. 1.1 May. 2003