K4S560432E-NC Datasheet, PDF (6/13 Pages) Samsung semiconductor – 256Mb E-die SDRAM Specification 54pin sTSOP-II

SDRAM 256Mb E-die (x4, x8)
CMOS SDRAM
PIN CONFIGURATION (Top view)
x8 x4
VDD
VDD
1
DQ0
NC
2
VDDQ
VDDQ
3
NC
NC
4
DQ1
DQ0
5
VSSQ
VSSQ
6
NC
NC
7
DQ2
NC
8
VDDQ
VDDQ
9
NC
NC
10
DQ3
DQ1
11
VSSQ
VSSQ
12
NC
NC
13
VDD
VDD
14
NC
NC
15
WE
WE
16
CAS
CAS
17
RAS
RAS
18
CS
CS
19
BA0
BA0
20
BA1
BA1
21
AP/A10 AP/A10
22
A0
A0
23
A1
A1
24
A2
A2
25
A3
A3
26
VDD
VDD
27
x4 x8
54
VSS
VSS
53
NC
DQ7
52
VSSQ
VSSQ
51
NC
NC
50
DQ3
DQ6
49
VDDQ
VDDQ
48
NC
NC
47
NC
DQ5
46
VSSQ
VSSQ
54 PIN sTSOP(II)
45
NC
NC
44
DQ2
DQ4
43
VDDQ
VDDQ
300mil x 551mil
42
NC
NC
(7.62mm x 14.00mm)
41
VSS
VSS
(0.5 mm pin pitch)
40
NC
NC
39
DQM
DQM
38
CLK
CLK
37
CKE
CKE
36
A12
A12
35
A11
A11
34
A9
A9
33
A8
A8
32
A7
A7
31
A6
A6
30
A5
A5
29
A4
A4
28
VSS
VSS
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
CKE
Clock enable
A0 ~ A12
Address
BA0 ~ BA1 Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM
Data input/output mask
DQ0 ~ N
VDD/VSS
VDDQ/VSSQ
N.C/RFU
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12,
Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9)
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7)
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
Rev. 1.1 February, 2004