K4S510832M Datasheet, PDF (6/11 Pages) Samsung semiconductor – 16M x 8bit x 4 Banks Synchronous DRAM LVTTL

K4S510832M
Preliminary
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Operating current
(One bank active)
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0 mA
Precharge standby current in
power-down mode
Precharge standby current in
non power-down mode
ICC2P
ICC2PS
ICC2N
ICC2NS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P
ICC3PS
ICC3N
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
Operating current
(Burst mode)
Refresh current
ICC4
ICC5
IO = 0 mA
Page burst
4banks Activated
tCCD = 2CLKs
tRC ≥ tRC(min)
Self refresh current
ICC6 CKE ≤ 0.2V
Version
-75
-1H -1L
200
180 180
6
5
30
10
10
8
50
35
200
170 170
330
310 310
7
3
Unit Note
mA
1
mA
mA
mA
mA
mA
mA
1
mA
2
mA
3
mA
4
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S510832M-TC**
4. K4S510832M-TL**
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev. 0.2 Dec. 2001