M470L3224DT0 Datasheet, PDF (5/12 Pages) Samsung semiconductor – 256MB DDR SDRAM MODULE

M470L3224DT0
200pin DDR SDRAM SODIMM
Absolute Maximum Rate
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V_SS
V_IN, V_OUT
-0.5 ~ 3.6
V
Voltage on V_DD & V_DDQ supply relative to V_SS
V_DD, V_DDQ
-1.0 ~ 3.6
V
Storage temperature
T_STG
-55 ~ +150
°C
Power dissipation
P_D
12
W
Short circuit current
I_OS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
2.7
I/O Supply voltage
VDDQ
2.3
2.7
V
I/O Reference voltage
VREF
VDDQ/2-50mV VDDQ/2+50mV
V
1
I/O Termination voltage(system)
Input logic high voltage
V_TT
VREF-0.04
VREF+0.04
V
2
VIH(DC)
VREF+0.15
VDDQ+0.3
V
4
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
4
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.3
VDDQ+0.6
V
3
Input crossing point voltage, CK and CK inputs
VIX(DC)
1.15
1.35
V
5
Input leakage current
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current(Normal strengh driver)
;V_OUT = V_TT + 0.84V
IOH
-16.8
mA
Output High Current(Normal strengh driver)
;V_OUT = V_TT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver)
;V_OUT = V_TT + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver)
;V_OUT = V_TT - 0.45V
IOL
9
mA
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2.V_TT is not applied directly to the device. V_TT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.1 Jan. 2002