K7R163684B_06 Datasheet, PDF (5/19 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 QDRTM II b4 SRAM

K7R163684B
K7R161884B
512Kx36 & 1Mx18 QDR^TM II b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7R161884B(1Mx18)
1
2
3
4
5
6
7
8
9
10
11
A
CQ NC/SA* NC/SA*
W
BW1
K
NC
R
SA NC/SA* CQ
B
NC
Q9
D9
SA
NC
K
BW0
SA
NC
NC
Q8
C
NC
NC
D10
VSS
SA
NC
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes: 1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 3A for 36Mb, 10A for 72Mb and 2A for 144Mb.
2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-17
Q0-17
W
R
BW0, BW1
VREF
ZQ
VDD
VDDQ
VSS
TMS
TDI
TCK
TDO
NC
PIN NUMBERS
DESCRIPTION
NOTE
6B, 6A
Input Clock
6P, 6R
Input Clock for Output Data
1
11A, 1A
Output Echo Clock
1H
DLL Disable when low
9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D
3F,2G,3J,3L,3M,2N
Data Inputs
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E
2F,3G,3K,2L,3N,3P
Data Outputs
4A
Write Control Pin, active when low
8A
Read Control Pin, active when low
7B, 5A
Block Write Control Pin, active when low
2H,10H
Input Reference Voltage
11H
Output Driver Impedance Control Input 2
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply (1.8 V)
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply (1.5V or 1.8V)
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
10R
JTAG Test Mode Select
11R
JTAG Test Data Input
2R
JTAG Test Clock
1R
JTAG Test Data Output
2A,3A,10A,7A,1B,5B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M
No Connect
3
2M,9M,1N,9N,10N,1P,2P,9P
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
Rev. 5.0 July 2006
-5-