K6X0808C1D Datasheet, PDF (5/9 Pages) Samsung semiconductor – 32Kx8 bit Low Power CMOS Static RAM

K6X0808C1D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=50pF+1TTL
CL¹⁾
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Parameter List
Read cycle time
Address access time
Chip select to output
Read
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
1. The parameter is tested with 50pF test load.
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
55¹⁾ns
70ns
Min
Max
Min
Max
55
-
70
-
-
55
-
70
-
55
-
70
-
25
-
35
10
-
10
-
5
-
5
-
0
20
0
30
0
20
0
30
10
-
10
-
55
-
70
-
45
-
60
-
0
-
0
-
45
-
60
-
40
-
50
-
0
-
0
-
0
20
0
25
25
-
30
-
0
-
0
-
5
-
5
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
Test Condition
Min Typ Max Unit
VDR
CS≥Vcc-0.2V
2.0
-
5.5
V
IDR
Vcc=3.0V, CS≥Vcc-0.2V
K6X0808C1D-F
-
-
10
µA
K6X0808C1D-Q
-
-
20
tSDR
tRDR
See data retention waveform
0
-
-
ms
5
-
-
5
Revision 1.0
December 2003