K4S561632A Datasheet, PDF (5/10 Pages) Samsung semiconductor – 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

K4S561632A
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Symbol
Test Condition
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0 mA
Version
Unit Note
-75 -80 -1H -1L
150 150 140 140 mA
1
Precharge standby current in
power-down mode
ICC2P CKE ≤ VIL(max), tCC = 10ns
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
2
mA
2
Precharge standby current in
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
16
non power-down mode
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
14
mA
Active standby current in
power-down mode
ICC3P CKE ≤ VIL(max), tCC = 10ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
6
mA
6
Active standby current in
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
35
mA
non power-down mode
(One bank active)
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
30
mA
Operating current
(Burst mode)
Refresh current
Self refresh current
IO = 0 mA
ICC4 ^{Page burst}
4banks Activated.
tCCD = 2CLKs
ICC5 tRC ≥ tRC(min)
ICC6 CKE ≤ 0.2V
180 180 145 145 mA
1
210 210 200 200 mA
2
C
5
mA
3
L
2
mA
4
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S561632A-TC**
4. K4S561632A-TL**
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev. 0.0 Sep. 1999