K4S281632M Datasheet, PDF (5/10 Pages) Samsung semiconductor – 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

K4S281632M
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Symbol
Test Condition
Burst length = 1
ICC1 tRC ≥ tRC(min)
IOL = 0 mA
CAS
Latency
Version
Unit
-80 -1H -1L -10
130 120 120 115 mA
Precharge standby current in
power-down mode
ICC2P
ICC2PS
CKE ≤ VIL(max), tCC = 15ns
CKE & CLK ≤ VIL(max), tCC = ∞
1
mA
1
Precharge standby current in
ICC2N
CKE ≥ VIH(min),CS ≥ VIH(min),tCC=15ns
Input signals are changed one time during 30ns
15
non power-down mode
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
7
mA
Active standby current in
power-down mode
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC = 15ns
CKE & CLK ≤ VIL(max), tCC = ∞
5
mA
5
Active standby current in
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns.
30
mA
non power-down mode
(One bank active)
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
20
mA
Operating current
(Burst mode)
IOL = 0 mA
ICC4 Page burst
tCCD = 2CLKs
3
170 145 145 145
mA
2
135 145 135 135
Refresh current
Self refresh current
ICC5
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
200
165 mA
C
1.5
mA
L
800
uA
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S281632M-TC**
4. K4S281632M-TL**
Note
1
1
2
3
4
Rev. 0.0 Aug. 1999