S1L9226X Datasheet, PDF (45/56 Pages) Samsung semiconductor – RF AMP & SERVO SIGNAL PROCESSOR

RF AMP & SERVO SIGNAL PROCESSOR
FOCUS OFFSET CONTROL
PRELIMINARY
S1L9226X
FSI 11
FGD 10
FSET
8
3.6K
60K
- _FZC
+^I
20K 48K
DFCTI _FS4B
Focus Phase
Compensation
FS2B
82K
40K
FS3
580K
470K 40K
PS
43
X1 0 0
X2 0 1
X3 1 0
X4 1 1
10K
50K
-
+
5K
FS1
9
7
FLB
FRCH
VC
-
+
to Digital
-
31 FEO
+
30 FEM
Focus Offset control starts when it receives the Focus Offset control start command $842X from micom. Focus
Offset control ends when the focus error amp output below 1/2VCC after the focus output with 1/2 VCC at the focus
error amp final output terminal. The voltage per 1 step of the focus offset control is approximately 40mV. The 4 bit
resistance DAC changes from 320mV up to -320mV in 1 step, after which 1/2 step, approximately -20ms offset, is
applied. The offset dispersion after Focus offset control exists between -20mV - +20mV. The Febias Offset can be
changed in 10mV step within the micom's ± 100mV range after focus offset control. The required per 1 step is
2.5ms; for 4 bits and total of 16 steps, the maximum required time is 128ms.
For focus offset readjust, 4-bit DAC is reset by $867, and reset can be canceled only when the $86FX applied D3
bit is changed from 0 → 1. The Febias DAC latch block reset for electrostatics and operation error is reset by
micom DATA and not by RESET terminal, the system reset.
5