K4S510432M Datasheet, PDF (4/11 Pages) Samsung semiconductor – 512Mbit SDRAM 32M x 4bit x 4 Banks Synchronous DRAM LVTTL

K4S510432M
PIN CONFIGURATION (Top view)
Preliminary
CMOS SDRAM
VDD 1
N.C 2
VDDQ 3
N.C 4
DQ0 5
VSSQ 6
N.C 7
N.C 8
VDDQ 9
N.C 10
DQ1 11
VSSQ 12
N.C 13
VDD 14
N.C 15
WE 16
CAS 17
RAS 18
CS 19
BA0 20
BA1 21
A10/AP 22
A0 23
A1 24
A2 25
A3 26
VDD 27
54 VSS
53 N.C
52 VSSQ
51 N.C
50 DQ3
49 VDDQ
48 N.C
47 N.C
46 VSSQ
45 N.C
44 DQ2
43 VDDQ
42 N.C
41 VSS
40 N.C/RFU
39 DQM
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
CKE
Clock enable
A0 ~ A12
Address
BA0 ~ BA1 Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM
Data input/output mask
DQ0 ~ 3
VDD/VSS
VDDQ/VSSQ
Data input/output
Power supply/ground
Data output power/ground
N.C/RFU
No connection
/reserved for future use
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9,CA11,CA12
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
Rev. 0.2 Dec. 2001