S5L9290X02 Datasheet, PDF (39/47 Pages) Samsung semiconductor – DIGITAL SIGNAL PROCESSOR FOR INTERNET AUDIO

DIGITAL SIGNAL PROCESSOR FOR INTERNET AUDIO
S5L9290X02
SIGMA-DELTA STEREO DAC
As a digital-to-analog converter that uses the ∑ ∆ modulation, the DAC installed in S5L9290X02 is composed of
the digital attenuation, de-emphasis filter, FIR filter, SINC filter, digital sigma-delta modulator, analog post-filter,
anti-Image filter etc. Normal input/output characteristics exist at 20kHz. It has SNR (Signal to Noise Ratio) above
90dB.
Timing Chart
LRCHI
BCKI
SADTI
Fs = 32/44.1/48kHz
12
24 25
48 1
R-CH (MSB) 15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L-CH (MSB) 15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32/44.1/48kHz Sampling Frequency (Fs) Support
If the DAC master clock is applied to 384 × Fs cycle, it supports 3 sampling frequencies.
If the command register $94's MSCKSW is "H" and command register $A9's RFCK_OEN is "L", the external
master clock can be applied to the RFCK terminal.
X1, X2 Speed Support
If the command register $F0's DFCK is set to "H", the internal data input rate becomes 2*Fs and the speed
becomes 2X.
Application Circuit
1uF
0.1uF 10uF 0.1uF 10uF 0.1uF 10uF
100K
1uF
100K
0.1uF 10uF
Lch
Rch
39