S1D2502B01 Datasheet, PDF (36/61 Pages) Samsung semiconductor – VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS

Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502B01
ADDRESSING
• Display RAM Structure
Display RAM Address Area
Row
0 0 ^{. . . . .. .}
1 32
2 64
3 96
..
..
..
..
Row Attribute Register
Virtual Register
29 30 31
61 62 63
93 94 95
125 126 127
.. .
.. .
.. .
.. .
14 ₄₄₈ . . . . . . .
15 480 481 482 483 484 ... 495 496
477 478 479
511
Frame/V-AMP Control Registers
Figure 12. Display RAM Structure & Monitor Display Position
Whereas F‘ igure 9. Memory Map of Display Registers’showed a logical configuration, the Figure above shows a
1KByte SRAM (512 × 16 bit)'s practical and physical configuration. For facilitating internal calculations, addressing
is done using exponents of 2, and the rows to the right of the 'Row Attribute Registers', excepting only IFF(255),
are 'Virtual Registers' that are not used.
If you set 'Frame Control Register 0's 'Erase' bit to '1', 480 areas are erased (excepting only the 16th line) in the
Figure above, and the 'Erasing Time' is measured with 480 areas as the standard.
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