S3F8647 Datasheet, PDF (353/399 Pages) Samsung semiconductor – 8-bit single-chip CMOS microcontroller

S3C8639/C863A/P863A/C8647/F8647
DDC MODULE
DDC DATA SHIFT REGISTER (DDSR)
The DDC data shift register for DDC interface, called DDSR, is located at F1H in set 1, bank 1. It is read/write
addressable. The transmitted data output serially from most significant bit (MSB) after writing a data to DDSR. In
addition, the received data from the IIC-bus input to DDSR serially from least significant bit (LSB). DDSR register
capable to write while DCSR0.4 is set to "1" and DCON.3 is set to "0", and to read anytime regardless of
ICSR0.4.
MSB .7
DDC Data Shift Register (DDSR)
F1H, Set 1, Bank 1, R/W
.6 .5 .4 .3 .2 .1
.0 LSB
8-bit data shift register for DDC Tx/Rx operations:
Write enable when DCSR0.4 is "1" and DCON.3 is
"0". Read enable anytime.
Figure 17-5. DDC Data Shift Register (DDSR)
17-7