K9K2G08X0A Datasheet, PDF (31/38 Pages) Samsung semiconductor – FLASH MEMORY

K9K2G08U0A
K9K2G08R0A
Figure 7. Random Data Output In a Page
R/B
RE
I/Ox
tR
00h
Address
5Cycles
30h
Col Add1,2 & Row Add1,2,3
Data Output
FLASH MEMORY
05h
Address
2Cycles
E0h
Data Output
Data Field
Spare Field
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2112, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array(
1time/16byte). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading
period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the
loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial
data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered to read the status register. The system controller can detect the completion of a program
cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset com-
mand are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
R/B
tPROG
I/Ox
80h
Address & Data Input
10h
70h
Col Add1,2 & Row Add1,2,3
Data
"0"
I/O0
Pass
"1"
Fail
31