K7R643682M_07 Datasheet, PDF (3/20 Pages) Samsung semiconductor – 2Mx36 & 4Mx18 & 8Mx9 QDR II b2 SRAM

K7R643682M
K7R641882M
K7R640982M
2Mx36 & 4Mx18 & 8Mx9 QDR^TM II b2 SRAM
2Mx36-bit, 4Mx18-bit, 8Mx9-bit QDR^TM II b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future fre-
quency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/
-0.1V for 1.8V I/O.
• Separate independent read and write data ports
with concurrent read and write operation
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed early write.
• Registered address, control and data input/output.
• DDR (Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks (K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write function.
• Separate read/write control pin (R and W)
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 15x17mm
& Lead Free
Org.
Part
Number
Cycle Access
Time Time
Unit
RoHS
Avail.
K7R643682M-F(E)C(I)25 4.0 0.45 ns √
X36 _{K7R643682M-F(E)C(I)20 5.0 0.45 ns √}
K7R643682M-F(E)C(I)16 6.0 0.50 ns
•
K7R641882M-F(E)C(I)25 4.0 0.45 ns √
X18 _{K7R641882M-F(E)C(I)20 5.0 0.45 ns √}
K7R641882M-F(E)C(I)16 6.0 0.50 ns
•
K7R640982M-F(E)C(I)25 4.0 0.45 ns √
X9 _{K7R640982M-F(E)C(I)20 5.0 0.45 ns √}
K7R640982M-F(E)C(I)16 6.0 0.50 ns
•
* -F(E)C(I)
F(E) [Package type]: E-Pb Free, F-Pb
C(I) [Operating Temperature]: C-Commercial, I-Industrial
FUNCTIONAL BLOCK DIAGRAM
36 (or 18, 9) _DATA
D (Data in)
REG
20 (or 21, 22) _ADD
ADDRESS
REG
R
W
BWX
CTRL
4(or 2) ^LOGIC
36 (or 18,9)
36 (or 18, 9)
20
(or 21,22)
WRITE DRIVER
2Mx36
(4Mx18)
MEMORY
ARRAY
72
(or 36,
18)
K
K
CLK
GEN
C
SELECT OUTPUT CONTROL
C
72
(or 36,
18)
Notes: 1. Numbers in ( ) are for x18 device, x9 device also the same with appropriate adjustments of depth and width.
36 (or 18, 9)
Q (Data Out)
CQ, CQ
(Echo Clock out)
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
Rev. 1.3 March 2007
-3-