K4S280432E Datasheet, PDF (3/14 Pages) Samsung semiconductor – 128Mb E-die SDRAM Specification

SDRAM 128Mb E-die (x4, x8, x16)
CMOS SDRAM
8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
The K4S280432E / K4S280832E / K4S281632E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x
8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
K4S280432E-TC(L)75
K4S280832E-TC(L)75
K4S281632E-TC(L)60/75
Orgainization
32M x 4
16M x 8
8M x 16
Max Freq.
133MHz
133MHz
166MHz
Interface
LVTTL
LVTTL
LVTTL
Package
54pin TSOP
54pin TSOP
54pin TSOP
Organization
32Mx4
16Mx8
8Mx16
Row Address
A0~A11
A0~A11
A0~A11
Column Address
A0-A9, A11
A0-A9
A0-A8
Row & Column address configuration
Rev. 1.4 February. 2004