K4R271669E Datasheet, PDF (3/20 Pages) Samsung semiconductor – 128Mbit RDRAM(E-die)

K4R271669E
Direct RDRAM^™
Overview
The RDRAM^ device is a general purpose high-perfor-
mance memory device suitable for use in a broad range of
applications including communications, graphics, video and
any other application where high bandwidth and low latency
are required.
The 128Mbit RDRAM devices are extremely high-speed
CMOS DRAMs organized as 8M words by 16. The use of
Rambus Signaling Level (RSL) technology permits 800MHz
transfer rate while using conventional system and board
design technologies.
RDRAM devices are capable of sustained data transfers at
1.25 ns per two bytes (10ns per sixteen bytes).
The architecture of the RDRAM devices allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The RDRAM device's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and communi-
cations include power management and byte masking.
Features
♦ Highest sustained bandwidth per DRAM device
- GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
♦ Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦ Advanced power management:
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
♦ Organization: 1Kbyte pages and 32 banks
♦ Uses Rambus Signaling Level (RSL) interface for up
to 800MHz operation
♦ WBGA package(54 Balls)
SEC 240 xCS8
K4R271669E
Figure 1: Direct RDRAM CSP Package
The 128Mbit RDRAM devices are offered in a horizontal
center-bond fanout CSP package.
Key Timing Parameters/Part Numbers
Speed
Organization
Bin
I/O
Freq.
MHz
t_RAC
(Row
Access
Time) ns
Part Number
256Kx16x32s^a -CS8 800
256Kx16x32s -CS8 800
45
K4R271669E-T^bCS8
45
K4R271669E-R^cCS8
a. “32s” - 32 banks which use a “split” bank architecture.
b. “T” - Lead free consumer package.
c. “R” - Leaded consumer package.
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Version 1.4 July 2002