K4D263238E Datasheet, PDF (3/17 Pages) Samsung semiconductor – 1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL

K4D263238E-GC
128M GDDR SDRAM
1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• VDD/VDDQ = 2.8V ± 5% for -GC25
• VDD/VDDQ = 2.5V ± 5% for -GC2A/33/36/40/45
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3, 4, 5 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 400MHz
• Maximum data rate up to 800Mbps/pin
ORDERING INFORMATION
Part NO.
Max Freq.
K4D263238E-GC25
400MHz
K4D263238E-GC2A
K4D263238E-GC33
K4D263238E-GC36
K4D263238E-GC40
K4D263238E-GC45
350MHz
300MHz
275MHz
250MHz
222MHz
K4D263238E-VC is the Lead Free package part number.
Max Data Rate
800Mbps/pin
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
444Mbps/pin
Interface
SSTL_2
(VDD/VDDQ=2.8V)
Package
SSTL_2
(VDD/VDDQ=2.5V)
144-Ball FBGA
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238E is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by
32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 3.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
-3-
Rev 1.7 (Nov. 2003)