BL8531H Datasheet, PDF (20/30 Pages) Samsung semiconductor – AFE FOR CCD/CIS SIGNAL PROCESSOR

AFE FOR CCD/CIS SIGNAL PROCESSOR
CLAMP LEVEL DECISION FOR EACH INPUT
* Assume that PGA gain = 1
* This flow chart is not fixed, but recommended.
User can modify this algorithm.
BL8531H
Write CIS clamp control register
Set to (111)
Decrease CIS clamp control
register by 1
Scan clamp level input
[Repeatedly, scan clamp level.
Average ADC output]
MIN(ADC output)
YES
> 204
NO
Increase CIS
clamp control
register by 1
NO
ADC output > 0
YES
Scan dark line
[MIN(ADC output) = Minimum value of all pixels]
YES
[(100mV)/(4V) * 4096 - 1 = 102]
MIN(ADC output)
> 102
NO
MIN(ADC output)
NO
>0
YES
Decrease CIS
clamp control
register by 1
Scan dark line
Increase CIS
clamp control
register by 1
Go to calibration
NO
MIN(ADC output)
> 102
YES
Increase CIS
clamp control
register by 1
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