KM732V688 Datasheet, PDF (2/15 Pages) Samsung semiconductor – 64Kx32 Synchronous SRAM

KM732V688/L
PRELIMINARY
64Kx32 Synchronous SRAM
64Kx32-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD=3.3V-5%/+10% Power Supply
• I/O Supply Voltage : 3.3V-5%/+10%
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a
linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 1cycle Disable.
• L-Level Three-State Output.
• 100-QFP-1420C
• 100-TQFP-1420A
FAST ACCESS TIMES
Parameter
Cycle Time
Symbol -13 -15 Unit
tCYC
13 15 ns
GENERAL DESCRIPTION
The KM732V688/L is a 2,097,152 bit Synchronous Static Ran-
dom Access Memory designed for high performance second
level cache of Pentium and Power PC based System.
It is organized as 64K words of 32 bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applica-
tions; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM732V688/L is fabricated using SAMSUNG′s high per-
formance CMOS technology and is available in a 100pin QFP/
TQFP package. Multiple power and ground pins are utilized to
minimize ground bounce.
Clock Access Time
tCD
7 7 ns
Output Enable Access Time
tOE
5 5 ns
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A′0~A′1
64Kx32
MEMORY
ARRAY
ADSP
CS1
CS2
CS2
GW
BW
WEa
WEb
WEc
WEd
OE
ZZ
DQa0 ~ DQd7
A0~A15
A0 ~ A1
ADDRESS
REGISTER
A2~A15
DATA-IN
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
-2-
Jun. 1998
Rev 2.0