KM416S8030B Datasheet, PDF (2/11 Pages) Samsung semiconductor – 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

KM416S8030B
CMOS SDRAM
Revision History
Revision 0.0 (May 15, 1999)
• Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.
• Skip ICC4 value of CL=2 in DC characteristics in datasheet.
• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.
• Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.
• Symbol Change Notice
Before
I_IL
Input leakage current (inputs)
I_IL
Input leakage current (I/O pins)
I_LI
I_OL
Output open @ DC characteristic table
Io
After
Input leakage current
Output open @ DC characteristic table
• Test Condition in DC CHARACTERISTIC Change Notice
Symbol
Before
After
I_{CC2P ,} I_CC3P
I_{CC2N ,} I_CC3N
I_CC4
CKE ≤ VIL(max), tCC = 15ns
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
2 Banks activated
CKE ≤ VIL(max), tCC = 10ns
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
4 Banks activated
Revision 0.1 (Jun 28, 1999)
• Added Notes @OPERATING AC PARAMETER
Notes : 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommands tRDL=2CLK and tDAL=2CLK + 20ns.
• Added -10 bining product.
Rev. 0.1 Jun. 1999