K7J161882B Datasheet, PDF (2/17 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 DDR II SIO b2 SRAM

K7J163682B
K7J161882B
512Kx36 & 1Mx18 DDR II SIO b2 SRAM
512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/
-0.1V for 1.8V I/O.
• Separate independent read and write data ports
• HSTL I/O
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• Full data coherency, providing most current data.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write (x18, x36) function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 13x15mm
Organization
Part
Number
Cycle
Time
Access
Time
Unit
K7J163682B-FC30 3.3
0.45 ns
X36
K7J163682B-FC25 4.0
0.45 ns
K7J163682B-FC20 5.0
0.45 ns
K7J163682B-FC16 6.0
0.50 ns
K7J161882B-FC30 3.3
0.45 ns
X18
K7J161882B-FC25 4.0
0.45 ns
K7J161882B-FC20 5.0
0.45 ns
K7J161882B-FC16 6.0
0.50 ns
FUNCTIONAL BLOCK DIAGRAM
36 (or 18) _DATA
D(Data in)
REG
18 (or 19) ADD
ADDRESS
REG
18
(or 19)
R/W
LD
BWX
CTRL
4(or 2) ^LOGIC
36 (or 18)
WRITE DRIVER
512kx36
(1Mx18)
MEMORY
ARRAY
36
(or 18)
K
K
CLK
C
GEN
C
SELECT OUTPUT CONTROL
Notes: 1. Numbers in ( ) are for x18 device
72
(or 36)
36
(or 18)
Q(Data Out)
CQ, CQ
(Echo Clock out)
DDR II SRAM and Double Data Rate II comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
-2-
July. 2004
Rev 3.1