K4S560432A Datasheet, PDF (2/10 Pages) Samsung semiconductor – 256Mbit SDRAM 16M x 4bit x 4 Banks Synchronous DRAM LVTTL

K4S560432A
16M x 4Bit x 4 Banks Synchronous DRAM
CMOS SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K cycle)
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The K4S560432A is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 x 16,785,216 words by 4 bits,
fabricated with SAMSUNG's high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
ORDERING INFORMATION
Part No.
K4S560432A-TC/L75
K4S560432A-TC/L80
K4S560432A-TC/L1H
K4S560432A-TC/L1L
Max Freq. Interface Package
133MHz(CL=3)
125MHz(CL=3)
100MHz(CL=2)
LVTTL
54pin
TSOP(II)
100MHz(CL=3)
Data Input Register
CLK
ADD
Bank Select
16M x 4
16M x 4
16M x 4
16M x 4
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 Sep. 1999