DS_M366S2953MTS Datasheet, PDF (2/9 Pages) Samsung semiconductor – PC133/PC100 Unbuffered DIMM

M366S2953MTS
PC133/PC100 Unbuffered DIMM
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
CKE
Clock enable
A0 ~ A12
Address
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9,CA11
BA0 ~ BA1 Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
VDD/VSS
Data input/output
Power supply/ground
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
REV. 0.0 Dec. 2001