S3F441FX Datasheet, PDF (193/233 Pages) Samsung semiconductor – 32-Bit CMOS RISC Microprocessor

S3F441FX RISC MICROCONTROLLER
SYSTEM MANAGER
EXTERNAL MEMORY CONTROL SPECIAL REGISTERS
MEMORY CONTROL REGISTER 0, 1, 2
Register
MEMCON0
MEMCON1
MEMCON2
Offset Address
0x4000
0x4004
0x4008
R/W
R/W
R/W
R/W
Description
Memory control register 0 (nCS0)
Memory control register 1 (nCS1)
Memory control register 2 (nCS2)
Reset Value
0800 3000h
0c08 3000h
100c 3000h
[1:0]
Reserved
Reserved to 00b
[4:2]
Tcos
000 = 0 cycles
011 = 3 cycles
110 = 6 cycles
001 = 1 cycles 010 = 2 cycles
100 = 4 cycles 101 = 5 cycles
111 = Not used
[7:5]
Tacs
000 = 0 cycles
011 = 3 cycles
110 = 6 cycles
001 = 1 cycles 010 = 2 cycles
100 = 4 cycles 101 = 5 cycles
111 = Not used
[10:8] Tcoh
000 = 0 cycles
011 = 3 cycles
110 = 6 cycles
001 = 1 cycles 010 = 2 cycles
100 = 4 cycles 101 = 5 cycles
111 = Not used
[13:11] Tacc
Memory access time(Tacc)
000 = Disable bank 001 = 2 cycles
011 = 4 cycles
100 = 5 cycles
110 = 7 cycles
111 = Not used
If nWAIT is used, Tacc ≥ 3
010 = 3 cycles
101 = 6 cycles
[15:14] Reserved
Reserved to 00b
[23:16] Base Address(BA)
Indicates Bank start address. User can configure bank size by 1MB
unit. If bank start address is 0x0100000, the base address(BA) field
value of this bank should be 0x01. The available range is 0-0x1e.
[31:24] End Address(EA)
Indicates Bank end address. If the end address of the bank is 0x0f3ffff,
the end address(EA) field value of this bank should be 0x10(
(0f3ffffh>>20) +1). The available range is 0x1-0x1f
NOTES:
1. nCS0 can be used for another external device if the In-ROM mode is selected by MD[1:0]=00b. If the nCS0 area is
overlapped with the internal flash memory, the internal flash ROM will be read by CPU.
2. nCS0 will be used for boot ROM if the external ROM mode is selected by MD[1:0]=01b.
9-5