M374F3200DJ1-C Datasheet, PDF (18/20 Pages) Samsung semiconductor – 32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V

DRAM MODULE
M374F320(8)0DJ1-C
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
VIH -
RAS
VIL -
tRP
tRAS
VIH -
CAS
VIL -
tCSR
tCHR
tCPT
tRSH
tCAS
tRAL
VIH -
A
VIL -
tASC
tCAH
COLUMN
ADDRESS
READ CYCLE
VIH -
W
VIL -
VIH -
OE
VIL -
tWRP tWRH
VOH -
DQ
VOL -
tRCS
tAA
tCAC
tRRH
tRCH
tCLZ
tOEA
tOEZ
DATA-OUT
tCEZ ^tWEZ
tREZ
WRITE CYCLE
VIH -
W
VIL -
VIH -
OE
VIL -
VIH -
DQ
VIL -
tWRP tWRH
tWCS
tRWL
tCWL
tWCH
tWP
tDS
tDH
DATA-IN
READ-MODIFY-WRITE
tWRP tWRH
VIH -
W
VIL -
VIH -
OE
VIL -
tRCS
tAWD
tCWD
tCAC
tAA
tOEA
tOED
tCWL
tRWL
tWP
tDH
VI/OH -
DQ
VI/OL -
tCLZ
tOEZ _tDS
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
Undefined
REV. 0.1 Oct. 2000