M368L1624DTM Datasheet, PDF (18/22 Pages) Samsung semiconductor – 184pin Unbuffered Module based on 256Mb D-die 64/72-bit Non ECC/ECC

128MB, 256MB, 512MB Unbuffered DIMM
DDR SDRAM
j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC ~ AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
Rev. 1.2 May. 2003