S3F9498 Datasheet, PDF (175/239 Pages) Samsung semiconductor – 8-BIT CMOS MICROCONTROLLER

TIMER 0
S3C9498/F9498
Timer 0 Control Register (TCCON)
You use the timer 0 control register, TCCON, to
— Enable the timer 0 operating (interval timer)
— Select the timer 0 input clock frequency
— Clear the timer 0 counter
— Enable the timer 0 interrupt
— Clear timer 0 interrupt pending conditions
TCCON is located at address D0H, and is read/write addressable using register addressing mode.
A reset clears TCCON to "00H". This sets timer 0 to disable interval timer mode, selects an input clock frequency
of fxx/1024, and disables timer 0 interrupt. You can clear the timer 0 counter at any time during normal operation
by writing a "1" to TCCON.3.
To enable the timer 0 interrupt , you must write TCCON.7, TCCON.2, and TCCON.1 to "1".
To generate the exact time interval, you should write TCCON.3 and TCCON.0, which cleared counter and interrupt
pending bit. To detect an interrupt pending condition when T0INT is disabled, the application program polls
pending bit, TCCON.0. When a "1" is detected, a timer 0 interrupt is pending. When the T0INT sub-routine has
been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending
bit, TCCON.0.
MSB .7
Timer C Control Register (TCCON)
D0H, Reset = 00H, R/W
.6 .5 .4 .3 .2 .1 .0 LSB
Timer 0 operation mode selection bit
0 = Two 8-bit timers mode (Timer C/D)
1 = One 16-bit timer mode (Timer 0)
Not used
Timer C interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
Timer C interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer C clock selection bits:
00 = fxx/1024
01 = fxx/512
10 = fxx/8
11 = fxx
Timer C counter enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer C counter clear bit:
0 = No affect
1 = Clear the timer C counter (when write)
Figure 13-1. Timer 0 Control Register (TCCON)
13-2