S6B0723 Datasheet, PDF (17/71 Pages) Samsung semiconductor – 132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.9
S6B0723
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There are CS1B and CS2 pins for chip selection. The S6B0723 can interface with an MPU only when CS1B is "L"
and CS2 is "H". When these pins are set to any other combination, RS, E_RDB, and RW_WRB inputs are disabled
and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter
are reset.
Parallel / Serial Interface
S6B0723 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or
serial interface is determined by PS pin as shown in table 8.
Table 8. Parallel / Serial Interface Mode
PS
Type
CS1B
CS2
H
Parallel
CS1B
CS2
L
Serial
CS1B
CS2
C68
Interface mode
H
6800-series MPU mode
L
8080-series MPU mode
*×
Serial-mode
*×: Don't care
Parallel Interface (PS = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in
table 9. The type of data transfer is determined by signals at RS, E_RDB and RW_WRB as shown in table 10.
Table 9. Microprocessor Selection for Parallel Interface
C68
CS1B
CS2
H
CS1B
CS2
L
CS1B
CS2
RS
E_RDB RW_WRB DB0 to DB7
MPU bus
RS
E
RW
DB0 to DB7
6800-series
RS
/RDB
/WRB
DB0 to DB7
8080-series
Common
RS
H
H
L
L
Table 10. Parallel Data Transfer
6800-series
E_RDB RW_WRB
(E)
(RW)
H
H
H
L
H
H
H
L
8080-series
E_RDB RW_WRB
(/RDB) (/WRB)
L
H
H
L
L
H
H
L
Description
Display data read out
Display data write
Register status read
Writes to internal register (instruction)
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